This invention relates to Basic Input/Output System (BIOS) operations and, more particularly, to executing large device firmware programs including device drivers, such as those stored in a read-only memory (ROM).
The BIOS is a firmware-resident program that initializes a platform following power-on or reset operations. Various components of the platform are initialized, one by one, after which the operating system is booted. The BIOS is stored on a firmware device such as a read-only memory (ROM), erasable program ROM (EPROM), or a flash memory device.
Some components of the system may not be recognized by the BIOS. Some hardware devices, for example, are controlled by a non-BIOS program stored on an expansion ROM, also known as an option ROM.
For some platforms, i.e., those which support Intel architecture processors, or those which are advanced-technology (AT)- or extended-technology (XT)-compatible, the BIOS is addressed at a memory region between 0xe0000 and Oxfffff. Likewise, expansion ROMs are addressed somewhere between 0xc0000 and 0xe0000, a 128K “compatibility” region. Regardless of the architecture, however, the expansion ROMs must be located in certain designated memory range or region due to compatibility reasons.
Typically, such platforms include a 32K expansion ROM dedicated wholly to supporting a video card. Of the original 128K, just 96K of the expansion ROM space is available for other expansion ROMs.
As new hardware features are supported or as hardware devices become more complex, the size of expansion ROMs tend to increase. For example, a single expansion ROM image may be expected to support many variations of the hardware. Therefore, an expansion ROM image may ideally implement a variety of desired new hardware features that take advantage of the latest hardware without needing removal of existing or older versions of code. In addition, the expansion ROM is desired to be backward compatible and platform independent.
In recognition of the limited space available for expansion ROMs, the Peripheral Component Interconnect (PCI) Bus Specification, Version 2.0, for one, introduced a mechanism for maximizing the use of space. The PCI Specification is available from The PCI Special Interest Group, Portland, Oreg. 97214. Under PCI 2.0, expansion ROMs are divided into initialization and runtime portions, although packaged into a single binary image. The initialization portion is executed, and subsequently discarded, while the runtime portion is maintained in the 128K expansion ROM region. In essence, the size of the expansion ROM stored in the expansion ROM region shrinks following initialization. However, increasingly enhanced expansion ROM support within the BIOS is desired.
Unfortunately, expansion ROMs have attained sizes of 80K to 90K and higher. Further, the ratio of initialization code to runtime code has increased, rendering the above solution impractical, in some environments. Where the initialization portion of the expansion ROM cannot be loaded into the designated expansion ROM memory, the fact that the expansion ROM shrinks following initialization is irrelevant.
Thus, there is a continuing need to support larger expansion ROMs on some platforms.